The
Etch Component of the Copper Interconnect Sequence
Definition
Interconnect: 1. to connect or be connected with each other, 2. conductor
line that can be created at successive levels on a silicon wafer
by etching vias and trenches in non-conducting materials and then
filling them with copper, aluminum, or other metal, 3. advanced silicon
integrated circuit wiring created by embedding copper in insulating
materials with low dielectric constant values to create the fastest
chips on Earth.
Importance to the Industry
Advanced technology demands extremely high routing density. In meeting
this demand, copper low-k interconnect is vital to the semiconductor
industry as the enabler of faster, smaller devices. Copper is a better
conductor and generally more robust than aluminum. Its resistance
is approximately 60% that of aluminum, which allows microprocessors
to operate up to 15% faster. For the same current, copper conductive
lines can be made smaller and thinner than aluminum lines, which,
in turn, make possible much denser transistor packing on individual
chips. In addition, copper is more than 50 times more resistant to
electromigration induced by the high electric currents needed for
fast circuit switching; hence it delivers more durable, reliable
devices.
Interconnected products, interconnected people… Applied
Materials understands the interconnect challenges like no one else.
The Etch Component of the Copper Interconnect Sequence
Dielectric etch is the most complex component of the copper interconnect
manufacturing sequence. Moreover, it can be repeated as many times
as necessary, depending on the number of metal layers needed to create
a specific device.
Dual damascene is the dielectric etch approach most widely implemented
today for copper interconnect. A wide variety of applications (e.g.,
DRAM, ASIC, MPU, and SOC) involve the damascene sequence. Damascene
refers to the process by which a metal conductor pattern is embedded
within a non-conducting (dielectric) material. In dual damascene
the process sequentially creates embedded vias and trenches,
with the vias forming the vertical connections from one layer of
circuitry (trenches) to the next. Etching the vias and trenches in
the dielectric materials avoids difficulties associated with etching
copper, instead filling the etched features with copper through a
sequence of processes known as metallization.
The progressive miniaturization of semiconductor devices has brought
with it a succession of technological complexities. The transition
from the 130nm node to 90nm and beyond is prompting use of a greater
diversity of dielectric materials and filmstacks than were previously
encountered. The proliferation is prompted partly by the need for
new materials as the physical and electrical properties of earlier
ones reach their limits and partly in an attempt to overcome the
major issues of resist and low-k fragility, and the photoresist poisoning
to which the newer films are highly susceptible.
A multi-layer photoresist/mask pattern transfer scheme can be used
to minimize etch-induced photoresist damage. Here the pattern from
the photoresist mask is transferred to an intermediate mask of more
robust material that is then used to pattern the underlying dielectric
material. This makes for better optical resolution. It also separates
pattern definition and plasma resistance functions: the photoresist
can be optimized for lithographic patterning while the intermediate
mask can be optimized for resistance to the plasma etch process.
The more robust layer can function as an anti-reflective coating,
and/or a planarizing layer, when patterning over previously etched
features, as in the case of dual damascene etch. By choosing the
intermediate mask material for its plasma resistance, the profile
and CD of the etched features can be more tightly controlled, and
the risk of resist poisoning, striations, and pattern deformation
reduced.
The variety of incoming filmstacks is, in turn, giving rise to different
DD etch approaches. These are:
Organic (typically
double layer) or inorganic sacrificial material
Multi-layer
resists
Metal hard
mask
Determining which one of these approaches to adopt involves many
factors: cost (both in process complexity and materials cost); extendibility
of the technology; performance tradeoffs; usability of current toolset;
and the nature of the learning curve to be encountered.
Depending on the approach adopted, several challenges arising from
progressively smaller feature scale will be faced to a greater or
lesser degree. Chief among these are maintaining resist integrity;
ensuring damage-free processing, especially of low-k films; delivering
consistent results over extended runs; and productivity.
Once the dual damascene structure has been etched and cleaned, the
wafer passes on to the metallization stage. Physical integrity of
the film and quality of post-etch topography are of paramount concern
to metallization. The first is important as the film must be able
to withstand chemical mechanical planarization. The second affects
adhesion of the copper barrier. If sidewalls are smooth and continuous,
with no breaks or inverted slopes, copper barrier deposition has
a large process margin. Imperfections, such as “veiling, “bat
wings,” dishing, or microtrenching can detract from electro
chemical deposition, creating discontinuities that pose the risk
of copper diffusion into low-k film and, ultimately, of device failure.
Organic Sacrificial Material (Dual-Layer BARC)
This method, commonly used for 130nm, is relatively straightforward
for lithography and etch processes and is, therefore, less costly
than other schemes. Here, the incoming wafer is patterned for via
etch, which is followed by ashing to remove the photoresist and its
underlying BARC layer. The first new layer of bottom anti-reflective
coating (BARC) is deposited and then removed, leaving the vias partially
filled. A second layer of BARC is deposited and patterned for trench
etch. As the trench is being etched, the via fill provided by the
first BARC layer protects the sidewalls. The wafer is ashed again
after the trench is etched, and, lastly, the barrier layer (partially
opened during the initial via etch) is completely opened to the copper-filled
trench below.
Inorganic Sacrificial Material
This approach involves the fewest steps as it generally uses only
one layer of sacrificial material. The incoming wafer is patterned
for via etch, which is followed by ashing to remove the photoresist
and its underlying BARC layer. The inorganic sacrificial film is
then deposited and patterned for trench etch. Some of the sacrificial
material remains in the bottom of the via following the trench etch
and is then removed with a wet clean before the barrier layer (partially
opened during the initial via etch) is completely opened to the copper-filled
trench below.
Triple-Layer Resist
This more complex and relatively costly process is, nevertheless, attractive
due to larger process window it allows for lithography and etch processes.
A via-patterned wafer is etched and ashed to remove the photoresist
and its underlying layer of BARC. The new layer of BARC is deposited
and overlain with successive layers of hard mask and
another layer of BARC, forming the “triple-layer” referred
to in this method’s name. A hard mask open etch opens the top
BARC and hard mask layers, after which the lower BARC
is opened and the trench is etched, leaving a partial BARC fill in
the bottom of the via. The remaining BARC layer and via fill are
removed in the subsequent ashing step, after which the barrier layer
(partially opened during the initial via etch) is completely opened
to the copper-filled trench below.
Metal Hard Mask
This method offers the best protection against resist poisoning and
works well for the porous low-κ films being introduced in pursuit
of ever-lower dielectric constants. However, it requires metal deposition
and etch systems in addition to dielectric systems and can pose greater
challenges for structural control and defect avoidance.
In this filmstack, the photoresist and its underlying BARC layer
are underlain by a layer of metal. The first step, therefore,
is a hard mask open to etch the trench width through this metal layer,
after which the wafer is ashed, exposing the remaining metal. Next,
BARC is deposited on it and patterned for via etch. This protects
the partial trench while the via width is etched to partially open
the barrier layer and the wafer is ashed again. BARC is deposited
once more and patterned for completing the trench etch. After the
trench is etched, BARC remaining in the bottom of the via is removed
in the ashing step before the barrier layer (partially opened during
the initial via etch) is completely opened to the copper-filled trench
below.
