As feature sizes shrink and device manufacturers look for ways to maximize the number of die per wafer, edge engineering has emerged as a way to improve overall die yield. The wafer edge is increasingly recognized as a potential source of yield-limiting defects, driving the need to optimize the quality of the edge. In addition, the need to improve productivity by increasing the number of die per wafer pushes the boundaries of the edge exclusion zone, shrinking them down to 1mm or less.

The Applied Inflexion Edge Polishing System takes edge cleaning to a new level by performing high-precision defect removal from the front and back side exclusion zones, as well as the bevel, apex, and notch regions. Inflexion clears all types of defects in a single pass, including film stack residues composed of both metals and dielectrics, which are difficult to remove by traditional cleaning methods. If not removed, these residues can flake off and be transferred to the active region during wafer handling and processing. Inflexion also effectively removes shallow surface defects, such as pits from the substrate, that can act as particle traps. At 45nm and beyond, both of these issues are expected to have a greater impact on device yield when immersion lithography processes are adopted into high-volume manufacturing. Eliminating these types of defects can potentially increase overall yield by up to 10%.^[1]

Leveraging Applied's extensive experience in wafer polishing technology, Inflexion uses an innovative abrasive tape technology to polish and clean the wafer's edge regions. With its proprietary polishing head design, Inflexion offers high-precision, tunable control for a broad range of film-to-wafer interface requirements, minimizing the exclusion area to maximize die per wafer.

Inflexion is configurable with up to three independent chambers. A three chamber system doubles the throughput of other commercial bevel polish technologies with production-proven results in front end of line and back end of line applications. The system employs Applied’s integrated post-polish Desica technology. The Desica cleaner uses unique full-immersion Marangoni vapor dry technology to virtually eliminate watermark defects for superior defect performance on both hydrophilic and hydrophobic surfaces.

Applied Inflexion:

• Removes all types of residues and defects from all wafer edge surfaces
• Allows tuning of the critical film-to-substrate transition region
• Offers parallel processing capability for high productivity

Application:

• Defect removal and high-precision edge engineering for logic and memory devices, supporting both FEOL and BEOL applications.

Learn More:
Wafer Edge Cleaning Technologies 
Wafer Edge Polishing Process for Defect Reduction during Immersion Lithography (SPIE 2008)

^[1]. J.D. Morillo et al., Edge and Bevel Automated Defect Inspection for 300mm Production Wafers in Manufacturing, Semiconductor Manufacturing Magazine, June 2005.