Applied Materials, Inc. - Conductor Deposition Technical Articles/Paper

Conductor Deposition Technical Articles/Papers

Aluminum Interconnect Solutions
Compensation of Overlay Errors Induced by Metal Sputter Deposition, Advanced Metallization Conference, 2005, pp 349-354 (419KB)

Extending Aluminum Via Fill Process to 50nm Technology Node With CVD Al Process Technology, SEMI® Technology Symposium at SEMICON® Korea, 2005 (128KB)

Advanced Al Contact Fill Investigations, Advanced Metallization Conference, 2004, pp 333-339 (1.19MB)

Applied Endura
Enhanced PVD Vacuum Pumping and Chamber Design Increases System Availability, Semiconductor Fabtech, 24th Edition (90KB)

Improving Defect Performance Through Better System Design, Nanochip Technology Journal, August 2004 (457KB)

This New Tool: Applied Materials’ Endura2, G. Dan Hutcheson, The Chip Insider™ from VLSI Research, June 2004 (278KB)

Contact Metallization Solutions
Contact Metallization for ≤ 45nm Devices, ECS-ISTC, 2005 (2.17MB)
Reproduced by permission of The ECS Asia, Inc. © The ECS Asia, Inc. International Semiconductor Technology Conference Proceeding “Semiconductor Technology” (ISTC 2005). All rights reserved. This work may not be reproduced, resold, distributed or modified without the express permission of The ECS Asia, Inc.

Powerful Quantitative Monitoring Tool Improves Cu and W Plug Fill, Nanochip Technology Journal, August 2004 (1.18MB)

ALD W Nucleation for ≤90nm Contacts, 2004 (1.09MB)

Copper Interconnect Solutions
Advanced Metallization Needs Integrate Copper Into Memory, Niranjan Kumar, Kevin Moraes, Murali Narasimhan and Prabu Gopalraja, Applied Materials Inc., Santa Clara, Calif., Semiconductor International, May 2008 (822KB)

Design Rule Considerations for RC Performance and Interconnect Reliability, Advanced Metallization Conference 2005, pp 623-628 (283KB)

Extending PVD Copper Barrier Process beyond 65nm Technology, Advanced Metallization Conference 2005, pp 421-427 (197KB)

Barrier Reliability of ALD TaN on Sub-100 nm Copper Low-k Interconnects, Advanced Metallization Conference, 2004, pp 801-805 (141KB)

Improvement in Parametric and Reliability Performance of 90nm Dual-damascene Interconnects Using Ar+ Punch-Thru PVD Ta(N) Barrier Process, Advanced Metallization Conference, 2004, pp 247-252 (441KB)

Improvement in Reliability of Cu Dual-Damascene Interconnects Using Cu-Al Alloy Seed, Advanced Metallization Conference, 2004, pp 221-226 (378KB)

ALD TaN Process Maintains Effective Line Resistivity for 65nm and Beyond, Nanochip Technology Journal, August 2004 (773KB)

Via Preclean Reduces CuO with Minimal Impact on k-Value, Nanochip Technology Journal, August 2004 (307KB)

ALD/PVD Barrier Reduces RC and Improves Reliability, Semiconductor International, June 2004†

Copper Challenges for the 45 nm Node, Semiconductor International, May 2004†

Re-Sputtering Improves Step Coverage, Reduces Rc, 2004 (838KB)

Device Packaging Metallization Solutions
Magnetron Sputtering of Nickel Silicon Alloy as Thin Film UBM for Pb-free Flip-Chip Packaging, Advanced Metallization Conference 2005, pp 185-189 (1.05MB)

Front End Metallization Solutions
Using PVD W/WN as a Gate Material, 2004 (1.48MB)

View Archive

† You will be leaving the Applied Materials Web site. The content of the third party Web site is not controlled by Applied Materials and this link is provided solely for your convenience.